1. Technical Field
The present invention relates in general to the verification of a digital circuit design and in particular to a method and system for verifying a digital circuit design utilizing timing analysis. Still more particularly, the present invention relates to a method and system for utilizing timing analysis to verify a digital circuit design including dynamic circuit cells that employ diverse circuit techniques.
2. Description of the Related Art
In a typical automated design process, such as that supported by a conventional electronic computer-aided design (ECAD) system, a designer enters a high-level design description utilizing either a hardware description language such as VHDL or interactively through the use of a schematic editor that produces a representation of the various circuit blocks and their interconnections. The ECAD system synthesizes a gate-level circuit design from the design description utilizing either predesigned circuit cells within a cell library or random logic macros (RLMs) generated directly from the design description. The gate-level circuit design is then typically verified to ensure that both functional and timing requirements of the circuit design are satisfied prior to developing a circuit layout (floorplan).
Conventional ECAD systems usually verify circuit designs comprised of static logic utilizing a rudimentary form of timing analysis that simply determines if the time required for a change in the state of an input to change the state of an output is less than the interval specified by the circuit designer. Although this method of circuit design verification is adequate for circuits implemented utilizing static logic, conventional timing analysis cannot adequately verify the operability of circuit designs comprising circuit cells that employ diverse circuit techniques, for example, both static and dynamic logic or multiple types of dynamic logic. Consequently, alternative methods of circuit verification, such as topological verification, must be utilized.
In topological verification, a set of rules is defined that specifies all permissible types of connections between circuit cells. Verification is accomplished by performing the relatively straightforward task of determining whether or not each circuit cell interconnection within the circuit design comports with the defined topological rules. In ECAD systems that utilize topological verification, only circuit designs in which all circuit cell connections satisfy the topological rules for all operating scenarios are verified as operable circuit designs. Thus, circuit designs including connections that are verifiable only if additional timing and signalling constraints are met are not successfully verified utilizing conventional topological verification. Thus, although topological verification has proved to be suitable for verifying conservative circuit designs, topological verification is less useful for high performance dynamic logic circuit designs since the strict topological rules impose unnecessary restrictions upon the types of connections that can be made within a circuit, thereby ruling out a number of useful connections that may be utilized to improve a circuit's performance characteristics. This is particularly true with reference to circuit designs including dynamic logical cells employing diverse circuit techniques and therefore having diverse functional and signalling constraints.
As should thus be apparent, it would be desirable to provide an improved method and system for verifying a digital circuit design, which support the verification of circuit designs including dynamic logic cells that employ diverse circuit techniques.